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T7000/Hardware - CPU P-states

From The Apple Wiki

As part of the PMGR block, there are 8 configurable CPU power states on the T7000. Hardware initialize state 0 to 24 MHz on reset. The state it is initialized in seems to be special in that in seems to bypass some clocks. SecureROM will (re-)initialize state 0 to 1, then switch to state 1. iBoot will initialize all the supported states, which may be different from model to model, then switch to state 2. iBoot seems to configure unused power states as the same as state 2.

Voltage control

Address 0x20e023c00 (32-bit):

This register appears to be some master voltage control register controlling whether changing the power states changes the voltage. Writing 1 to this register appears to enable the controls. iBoot appears to boot kernels with voltage controls disabled, making higher frequency states unusable. Bit 31 seems to be a busy bit, so poll until it is gone.

Set state

Address 0x202220020 (64-bit):

Bit Access Function
31 R Busy flag. After setting the power state, poll for this bit until it is gone.
25 W Needed to indicate to hardware that we are setting the state. Read as 0.
24-22 RW Desired state from 0-7.

Get state

Address 0x202220050 (32-bit):

Bit Access Function
0-2 R Target state
3-5 R Current state

State definition registers

Voltage and frequency definitions is stored in these registers and so it is possible to overclock the device by messing with them.

After changing these registers, the CPU is unaffected until the state is set using the set state registers.

Base address 0x202220068 (64-bit), one register for each of the 8 states, so the register for state N is 0x202220068 + (N * 8).

It is recommended to not touch state 0-2, as state 2 appears to be used for thermal throttling (probably configurable via other registers).

Registers

Bit Access Function
63-56 RW CPU Voltage. vol below.
55-49 RW Minor CPU voltage adjustment 3. Encoding unknown.
47-42 RW Minor CPU voltage adjustment 2. Encoding unknown.
41-36 RW Minor CPU voltage adjustment 1. Encoding unknown.
35-30 RW Minor CPU voltage adjustment 0. Encoding unknown.
17-13 RW Divider 1, div1 below
4-12 RW Frequency multiplier, mul below
0-3 RW Divider 2, div2 below

Formula

CPU frequency: ((24000000 * mul) / div1) / (div2 + 1) Hz

CPU Voltage: 600 + vol * (25 / 8) mV.

The minor voltage adjustment registers will also affect the voltage slightly.