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There is not a specific WDT device in 3GS device tree. The reboot sequence instead accesses several registers in PMGR.
LDR R1, =0xBF10021C LDR R3, =0xBF100214 MOVS R0, #0 MOVS R2, #1 STR R0, [R1] STR R2, [R3] LDR R2, =0xBF100210 MOV.W R3, #0x80000000 STR R3, [R2] MOVS R3, #4 STR R3, [R1] STR R0, [R2]
The MIU setup is found in the miu_init() in the LLB image instead. The register that contains MIU setting is 0xBF100000 (PMGR base address). The bit mask is now 3 instead of 7 for most other devices before this. Assume setting for map to 0x0 is 1, otherwise 2.
ROM:84006F44 CBZ R0, loc_84006F4C ROM:84006F46 CMP R0, #1 ROM:84006F48 BNE loc_84006F68 ROM:84006F4A B loc_84006F5A ROM:84006F4C loc_84006F4C ROM:84006F4C LDR R2, =0xBF100000 ROM:84006F4E LDR R3, [R2] ROM:84006F50 BIC.W R3, R3, #3 ROM:84006F54 ORR.W R3, R3, #1 ROM:84006F58 B loc_84006F66 ROM:84006F5A loc_84006F5A ROM:84006F5A LDR R2, =0xBF100000 ROM:84006F5C LDR R3, [R2] ROM:84006F5E BIC.W R3, R3, #3 ROM:84006F62 ORR.W R3, R3, #2 ROM:84006F66 ROM:84006F66 loc_84006F66 ROM:84006F66 STR R3, [R2] ROM:84006F68 ROM:84006F68 loc_84006F68 ROM:84006F68 LDR R3, =0xBF100000 ROM:84006F6A LDR R3, [R3] ROM:84006F6C BX LR